Description
SRL-LLC FPGA Triple-Speed Ethernet consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) intellectual property (IP). This IP function enables FPGAs to interface to an external Ethernet PHY device, which, in turn, interfaces to the Ethernet network.
The Triple-Speed Ethernet can use either serial interfaces (SGMII and 1000Base-X) or LVDS I/Os with dynamic phase alignment (DPA) that can operate up to 1.25 Gbps. The LVDS I/Os enable very scalable multi-port gigabit Ethernet (GbE) system designs while leaving serial transceivers for higher performance protocols.
